======  Regular meeting on 2017.12.20 ======
\\

===== Preliminary agenda =====

 General points in Wiki's dashboard:
  - Upcoming Tests - Planning
  - Results from Recent Tests - Analyzing/discussing
  - Common Test Infrastructure - Building
  - Other Activities & Resources

===== MoM =====

==== 1.  Attendees  ====

-- Alexander Pawlitzki (Thales-Alenia Space, Deutschland) \\
-- Dan Elftmann (Xilinx) \\
-- Kristianto (Kris) Hartojo (Radiation Test Solutions) \\
-- Eliot Glaser (Northrop Grumman) \\
-- Gary Swift (meeting moderator, Swift ERS) \\
-- Joseph (Joe) Marshall (BAE) \\
-- Kevin Wray (Boeing) \\
-- Mike Tostanoski (Radiation Test Solutions) \\
-- Mike Wirthlin (BYU) \\
-- Paul Nunnally (Xilinx FAE) \\
-- Ron Smith (Northrop Grumman) \\
-- Scott Arlo Anderson (SEAKR) \\
-- Sebastian Garcia (Slabs) \\
-- Steve Pearl (General Dynamics) \\
-- TAS-E (Thales-Alenia Space, España) team (Filip)\\

==== 2.  Topics covered ====

//NOTE: The following are very brief descriptions. Being this a Wiki, please complete/expand/correct them if you think we are missing interesting information (especially regarding anything important for future reference). 
//


**Mike Tostanoski and Kris Hartojo, both from Radiation Test Solutions, Colorado Springs, presented themselves.**
Mike is one of the owners of [[ http://www.radtestsolutions.com | Radiation Test Solutions]] business, an "off shoot" from the Cobham-Aeroflex RAD group. They perform SEE testing for Cobham RAD and other customers. Last year they were 7th on the list at TAMU for total hours use, and currently are moving up on that list. Having regular testing there once a month, doing across the board from 2-terminal devices to FPGAs. Right now, for FPGAs, they're having testing requirements for designs based on DDR3/DDR4 memory I/Fs.
Kris mentions also working on system-level and component-level analysis, with particular interest in Xilinx US and US+ parts for space use.

In the context of Xilinx' development card for the space Kintex US, Dan asks for opinions on which **DDR** generation the space users are mostly interested in (maybe based on SEFI modes or other criteria). 
Some comments from Kris, Eliot, Gary, Dan, Alexander, Filip. Summarizing, it seems this is not completely clear, but DDR3L may be the current "reasonable" target, considering requirements and trade-offs (more demanding onboard processing requirements, availability of COTS devices with high-bandwidth I/F stds., conservative design practices, etc.).
Gary mentions the V-5QV "CPU card" and the interest on a robust memory interface, to be able to perform in-beam tests of OSs running on a FPGA processor.


**Upcoming tests planning**. We are entering the usually test hiatus, facilities closing during the holidays and maintenance in January, past of February. Hoping to have the new test infrastructure ready for February. 
Kris comments that they have requested radiation time for next March.  

Gary mentions the intention to look at ** US+ latchup suppression using DD effect **. 
Needing some XRTC member to contribute a couple of hours of heavy-ion beam time, to test the latchup on the US+, for some parts (previously irradiated, for DD). Xilinx is providing parts for this.  There are doubts on whether the 'speed grade' of the chosen part may be relevant for this experiment (as we are targetting minority carriers' lifetime in the parasitic BJTs). 
Dan requests Gary to write an abstract of the test, with requirements for selecting the parts. 
The DD may be achieved from a 'candy bag' kind of test, using a high flux neutron beam at TRIUMPH. Also, some XRTC member may have access to a reactor and its fission spectrum neutrons. 
\\
Kris mentions that Cobham has a D-T irradiator providing 14 MeV neutrons **[1]**, but don't know how open they will be on donating some test time on some solid angles.
About the required fluences, Kris says that he can get 10^13 n/cm^2 within an hour or two. Gary says that by 10^14 we may have noticeable effects on electrical parameters. 
Kris says that an upside of using 14 MeV neutrons is that there's a lower TID than using the broad fission spectrum (around 2 MeV). A fluence of around 10^13 n/cm^2 is the minimum he considers required to kill the parasitic transistors "beta" gains. 

In addition to the main target for testing (Kintex UltraScale) we keep in mind **additional tests**:
  - Further dynamic and mitigation testing of the **Virtex-7 980T (28nm family)**, untested primitives:
    * IODelay test (ready to go),
    * Dynamic flip-flops,
    * DSPs (both static and dynamic),
    * MGTs (with and without protocol) (Boeing may share some recent results here soon);
  - ARM processor primitive tests;
  - MPSoC architecture explorations;
  - US+ latchup suppression experiment (as previously mentioned).

 
Progress on **Common Test Infrastructure**. 
Gary working on this last week. Turnover to STS the pin connection specifications for +90% of the new motherboard. The infrastructure team will be doing a revision and hopefully completing it in  tomorrow's telecon meeting. 
Xilinx has contributed NRE hours for schematic capture and board layout. 
Gary shows the mechanical diagram of the motherboard/backplane (with keep-out zone for the DUT card) that  attaches to the TAMU frame.
As a downside, due to the assymetry, the full boards assembly won't fit into TAMU's vacuum chamber, which is used in case of latchup testing (e.g., using "full-range" Au ions without loosing energy passing through mica and air). 
For this, it will be OK to just use the DUT card stand-alone (no FuncMon).
The next step will be to develop the DUT card for the KU060 part.

Next ** XRTC Annual meeting ** will be hosted in either San Jose or Longmont Xilinx facility. Will survey members about this in January regular telecons.
  
Sebas comment that, regarding the neutron fluence required for US+ latchup suppression experiment, in J. Karp's recent work **[2]** there's a simulation-based estimation for the parasitic transistors beta-product. This could be used as starting point for test planning purposes. 
Gary comment that we can even get to them to simulate the DD effect, and see what the values are then.
  
  
  
  
  
  

\\

**[1]** (Sebas' addition) In the following work, there's a brief description of Cobham's infrastructure: \\ 
//Neutron Induced Single Event Upset (SEU) Testing of Static Random Access Memory (SRAM) Devices,// 
M. Tostanoski et. al. \\
http://ieeexplore.ieee.org/document/7004579/ \\

**[2]** //Single Event Latch-up: Increased Sensitivity from Planar to FinFET,//  
James Karp, Michael J. Hart, Pierre Maillard, Geert Hellings, Dimitri Linten. \\
REDW-NSREC 2017. \\
http://ieeexplore.ieee.org/document/8141939/ \\



